74LVC2G74 Datasheet, flip-flop, NXP Semiconductors

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74LVC2G74 Features and benefits

I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.6.

74LVC2G74 Application

using IOFF. The IOFF circuitry disables the output, preventing damaging backﬂow current through the device when it is po.

74LVC2G74 Description

The 74LVC2G74 is a single positive-edge triggered D-type ﬂip-ﬂop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q outputs. This device is fully speciﬁed for partial power-down applications .

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